1. Field of the Invention
This invention relates in general to a semiconductor component which has at least one planar zone embedded in a surface of a semiconductor body and a first insulating layer on the surface of the semiconductor body and a channel stopper electrode formed on the first insulating layer at the edge of the semiconductor body 3 and an electrode that covers the pn-junction adjoining the planar zone formed on the first insulating layer. The electrode and channel stopper electrode are covered by a second insulating layer and a channel stopper field plate is formed on the second insulating layer which covers the channel stopper electrode at least on that portion facing away from the edge of the semiconductor body and is electrically connected to the channel stopper electrode. An anode field plate is formed on the second insulating layer and covers the electrode at least at that side facing away from the planar zone and is electrically connected to the planar zone and the two field plates are spaced apart and the second insulating layer is thicker in the region between the channel stopper field plate and the anode field plate.
2. Description of Related Art
FIG. 1 illustrates a prior art semiconductor component which has a semiconductor body 1 which has a top planar surface 8 in which a zone 2 is formed that has a conductivity type that is opposite to the semiconductor body 1. The semiconductor body 1 is limited by an edge 4 as shown. A first insulating layer 5 is arranged on the surface 8 and extends up to the edge 4 and covers the pn-junction 3 where it abuts the surface 8 on the side opposite the edge 4. A channel stopper field electrode 7 is formed on the first insulating layer starting adjacent the edge 4 of the semiconductor body and extends at its other edge over the pn-junction 3 between zone 2 and semiconductor body 1. An electrode 6 covers the first insulating layer 5 above the pn-junction 3. In the case of a MOS transistor, for example, the electrode 6 can be a gate electrode and can be connected to a gate terminal G.
A second insulating layer 9 is formed over the channel stopper electrode 7, the first insulation layer 5 and the electrode 6 as shown. A channel stopper field plate 11 which is electrically connected to the channel stopper electrode 7 is provided on the second insulating layer 9 adjacent the edge 4. An anode field plate 10 which overlaps the electrode 6 is formed on the second insulating layer 9 on the side which faces away from the edge 4. The inner edges of the field plates 10 and 11 are spaced from each other as shown. The surface of the second insulating layer 9 between the edges of field plates 10 and 11 is covered with a passivation layer 12. The passivation layer is formed of a poorly conductive material, for example, amorphous silicon. The amorphous silicon has a defined specific resistance so that a defined voltage curve can be maintained between the field plate 10 and the field plate 11. The field lines thus emerge from the opening between the field plates 10 and 11 and are uniformly distributed. With the thickness of the two insulating layers 5 and 9 which is relatively small, a relatively high blocking or offstate voltage for the semiconductor component can be obtained. A highly doped anode zone 15 is provided on the other side of the semiconductor body 1.
The specific resistance and the stability of the amorphous silicon are very difficult to reproduce and require extreme care during manufacturing processes.
Patents which are related to this invention are U.S. Pat. Nos. 3,767,981, 4,614,959, European Patent Application 069,429, German DE No. 351,622, German DE No. 3,141,203, German DE No. 3,046,749, European Patent No. 077,481 and the publication in IEEE Transactions on Electron Devices ED-33, 1986, December, No. 12, New York, N.Y. U.S.A. entitled "An Accurate DC Model For High Voltage Lateral DMOS Transistors Suited for CACD" Pages 1964-1970.